Description: 同步fifo设计,仿真已通过,用Verilog编写,代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short Platform: |
Size: 1024 |
Author:xinghuo |
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Description: 同步fifo设计,仿真已通过,用Verilog编写,代码短小,易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand Platform: |
Size: 1024 |
Author:xinghuo |
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Description: This application note describes how to build high-speed FIFOs using the Block SelectRAM+
memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The
design is for a 512x8 FIFO, but each port structure can be changed if the control logic is
changed accordingly. Both a common-clock version and an independent-clock version are
described. Platform: |
Size: 30720 |
Author:fjmwu |
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Description: 是用verilog HDL写的基于FIFO的串口发送机的设计,很详细的代码,很值得学习,已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by. Platform: |
Size: 359424 |
Author:张阳 |
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Description: 基于verilog HDL的fifo设计与测试,包含设计与测试代码,以及简单的makefile编写。整个平台是基于linux操作,仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation platform is based on the VCS of SYNOPSYS tools.) Platform: |
Size: 15360 |
Author:yzzls |
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